The design of integrated circuits (IC's) may involve a number of phases or steps as part of a design flow for IC design. Such design phases may include a system level design phase, digital and analog design phases, physical design and verification phases, and fabrication and packaging phases, among others. The IC design flow may also include a register transfer level (RTL) design phase that utilizes a hardware descriptive language (HDL) to provide functional models of components of an IC design. For example, it is known to provide automated tools which use a functional design of a planned IC (e.g., in the form of an RTL representation or a gate level netlist representation of the design) and a standard cell library in order to generate a circuit design (e.g., schematic and or layout representations) corresponding to the IC design.
The RTL design phase (and other phases of the IC design) may utilize various sequential elements as components of the IC. For example, sequential elements in RTL (e.g., elements declared as “reg” in a HDL such as Verilog) may be instantiated as flip-flop (FF) devices during the physical design phase (e.g., circuit implementation). The FF devices may be of different types (e.g., such as SR, JK, T and D) and are utilized as data structures for storing a data value. Typically a FF comprises one or more latches. For example, a FF may comprise a master latch and a slave latch. The circuitry that makes up a FF can also be clocked such that different parts of the FF circuitry may respond to a clock signal. The clocked FF may produce an output signal based on an input signal and the clock signal.
Flip-flop devices may be susceptible to soft errors that may be caused by the flip-flop's exposure to neutrons or alpha particles during operation. These soft errors may result in data values that are stored by the FF (e.g., data corresponding to logic values of 0 or 1) to be disturbed and/or lost. Flip-flop data failures due to these soft errors may correspond to a particular failure-in-time (FIT) rate for the FF which may be undesirably large for the IC design. Additionally, different FFs of an IC design may exhibit different soft error FIT rates. Current RTL design approaches cannot differentiate between FFs with different FIT rates. As such, current RTL design approaches cannot account for the use of different FFs in the IC design based on soft error FIT rates of sequential devices.
It would be advantageous to provide techniques to reduce the soft error FIT rates associated with sequential devices (e.g., FFs) of an IC design. Such a reduction may improve the performance and reliability of the IC design and its corresponding fabricated components. Furthermore, it would be advantageous to provide techniques for the differentiation and selection of different sequential devices as part of an RTL design phase so as to facilitate the reduction of soft error FIT rates associated with the IC design. Such techniques may improve the design efficiency and further reduce the costs associated with the design flow of the IC design.